The present invention relates generally to phase-locked loops, and more specifically relates to a modified first-order digital phase-locked loop which is configured to accommodate large frequency differences.
Typically, when data is read from a disk drive, a read channel chip inside the disk drive extracts an embedded clock signal from a data stream. The embedded clock signal which is extracted from the data stream is often referred to as the xe2x80x9crecovered clock.xe2x80x9d FIG. 1 illustrates typical waveforms of incoming data and a xe2x80x9crecovered clockxe2x80x9d in a disk drive read application.
Usually, an analog phase-locked loop (PLL) is used to extract the clock signal from the incoming data. Unfortunately, analog PLL""s present several disadvantages. For example, the performance of an analog PLL is typically quite sensitive to process, temperature and supply voltage variations. Additionally, the structure and characteristics of analog PLL""s typically often render it relatively difficult to effectively migrate to a new process technology. Still further, analog PLL""s are typically sensitive to noise.
Because analog PLL""s present certain disadvantages, some of which have been discussed above, it is sometimes advantageous to utilize a digital PLL instead of utilizing an analog PLL in disk drives. In fact, utilizing a simple first-order digital PLL to recover a clock signal from incoming data in a disk drive has proven to be very effective, so long as the difference in frequency between the local clock and the recovered clock is relatively small, such as approximately +/xe2x88x92100 p.p.m. (See, for example, Dao-Long Chen, xe2x80x9cA power and area efficient CMOS clock/data recovery circuit for high-speed serial interfacesxe2x80x9d, IEEE Journal of Solid-State Circuits, vol. 31, no. 8, August 1996).
A typical first-order digital PLL which is used in connection with a disk drive is illustrated in FIG. 2. As shown, the PLL 18 includes a data sampler 20 and a lead/lag phase detector 22 which receive incoming data (along leads. 21 and 23). The PLL 18 also includes a clock multiplexer 24 (identified in FIG. 2 as xe2x80x9cClock Muxxe2x80x9d), a digital loop filter 26 and a frequency synthesizer 30. The frequency synthesizer 30 receives a local reference clock (along lead 31) and includes a divider 32, a phase/frequency detector 34, a charge pump 36, a loop filter 38, a voltage-to-current converter 40 (identified in FIG. 2 as xe2x80x9cV to Ixe2x80x9d), a current-controlled oscillator 42 (identified in FIG. 2 as xe2x80x9cICOxe2x80x9d) and another divider 44.
In operation, the frequency synthesizer 30 uses the local reference clock to generate n clock phases, where the clock phases are generally equally spaced apart in time. The data sampler 20 receives the clock phases from the frequency synthesizer 30, and uses the clock phases to sample the incoming data. Based on the sampled results, one of the clock phases is selected as the recovered clock. For example, if the incoming data transitions from 0 to 1 between clock phase m and m+1, clock phase m is selected as the recovered clock.
Once a clock phase is selected, the data sampler 20 is disabled to conserve power. In the meantime, the PLL 18 switches to a data tracking mode, wherein the lead/lag phase detector 22 detects if the selected clock phase is leading or lagging the data whenever a data transition occurs. If the selected clock phase consistently lags the data (e.g. 6 out of 8 transitions), the PLL 18 will effectively replace phase m with phase mxe2x88x921 as the recovered clock. The loop filter 38 effectively controls how frequently the PLL 18 will act to update the recovered clock.
The PLL 18 illustrated in FIG. 2 will fail if there is a large frequency difference between the recovered clock and the local clock. For example, if there is a frequency 5% difference, and the PLL 18 has ten clock phases (i.e., n=10), each bit time will result in a phase shift equivalent to 0.5 of a clock phase. In other words, the PLL 18 will have to update the recovered clock every two bit times just to compensate for the frequency difference. As a result, the loop bandwidth will be too wide to reject any transient noise. In order to track the large frequency difference without introducing an excessive amount of jitter, a second-order digital PLL must be used. (See, for example, Lindsey et al., xe2x80x9cA survey of digital phase-locked loopsxe2x80x9d, Proceedings of the IEEE, vol. 69, no. 4, pp. 410-431, April 1981).
In removable disk drives, the frequency difference between the local clock and the recovered clock could be relatively large, such as +/xe2x88x922.5%, because the data could be written by another drive. Therefore, typically a second-order digital PLL must be used in connection with removable disk drives. Unfortunately, it is difficult to design a second-order digital PLL that can meet all the requirements of a disk drive application. (See, for example, Beomsup Kim, xe2x80x9cDual-loop DPLL gear-shifting algorithm for fast synchronizationxe2x80x9d, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 44, no. 7, pp. 577-586, July 1997). Furthermore, a second-order digital PLL is typically much more complex than a first-order digital PLL, and typically consumes more power and chip area.
Because a first-order digital PLL is less complex and consumes less power and area than does a second-order digital PLL, it would be advantageous to utilize a first-order digital PLL in a disk drive application in which the difference in frequency between the local clock and the recovered clock is expected to be relatively large.
It is an object of an embodiment of the present invention to provide a first-order digital PLL which is configured to accommodate large frequency differences between a local clock and a recovered clock.
It is a further object of an embodiment of the present invention to provide a first-order digital PLL which can be used in connection with removable disk drives.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a first-order digital PLL which is configured to accommodate a large frequency difference between a clock signal embedded in an incoming data stream received by the phase-locked loop and a local reference clock signal received by the phase-locked loop circuit. The PLL includes a data sampler which receives the incoming data stream, a frequency-locked loop (FLL) which receives the incoming data stream and is connected to the data sampler, and a frequency synthesizer which receives the local reference clock signal and is connected to the FLL. The FLL is configured to provide a first signal to the data sampler when no incoming data stream is received by the FLL, and the first signal has a frequency which is generally equal to the frequency of the local reference clock signal. The FLL is configured to provide a second signal to the data sampler when the FLL receives the incoming data stream, and the second signal has a frequency which is generally equal to the frequency of the incoming data stream.
Preferably, both the FLL and the frequency synthesizer include a phase/frequency detector, a charge pump connected to the phase/frequency detector, a loop filter connected to the charge pump, a voltage-to-current converter connected to the loop filter, and a current-controlled oscillator connected to the voltage-to-current converter. Preferably, the FLL is configured to disconnect the loop filter from the charge pump when no incoming data stream is received by the FLL. Preferably, the FLL is configured to connect the loop filter to the charge pump when the FLL receives the incoming data stream. Preferably, the current-controlled oscillator of the FLL is configured to selectively operate at the frequencies of the local reference clock signal and the incoming data stream and is configured to provide the first and second signals to the data sampler. Preferably, the FLL includes a switch between the charge pump and the loop filter, and includes a counter which receives the incoming data stream and is configured to control the switch. The incoming data stream preferably includes a synchronization field which precedes a data field, and preferably the FLL is configured to provide the second signal to the data sampler while the synchronization field is being received by the PLL.